Study of dynamics of charge trapping in a-Si:H/SiN TFTs

In this paper we present the study of the failure mechanism responsible for long-term degradation that ultimately leads to instability in aSi:H/SiN TFTs. The experimental data points we obtain by monitoring in-situ the drain current during gate bias stress (forward and reverse bias) and relaxation could not be fitted with the models existent in the literature. A new model that we have christened "Progressive Degradation Model" (PDM) emerged. The model makes use of Heimann-Warfield theory of trapping/detrapping front. PDM achieves a consistent fit to any bias condition showing that the degradation can be modelled quantitatively yielding the number of traps involved, their position and the charge dispersion coefficient. According to PDM the degradation of electrical response is a combined effect of a fast interface traps generation and a slow charge trapping at the created defect sites in a-SiN:H transitional region.